Frequency divider monitor of phase lock loop

ABSTRACT

A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

RELATED APPLICATIONS

This application is a continuation of and claims priority of copendingU.S. patent application Ser. No. 11/276,410 filed on Feb. 28, 2006.

FIELD OF THE INVENTION

The present invention relates to the field of frequency dividercircuits; more specifically, it relates to methods and circuits formonitoring the operation frequency of the divider circuits.

BACKGROUND OF THE INVENTION

In modern integrated circuits and electronic systems, clock signals aregenerated using phase lock loop circuits that use frequency feedback togenerate a clock signal with stable frequency value and constant phaseperformance. Frequency dividers are one of the most prone to failurecomponents of the high speed phase lock loops. In one failure mode, theoutput frequency of the frequency divider changes from design or drifts.In such a case, the integrated circuit or electronic system to which theclock signal is supplied can malfunction. Therefore, there is a need formethods and circuits for monitoring operation of the frequency dividersof integrated circuits and electronic systems.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a circuit, comprising: aphase locked loop circuit including a voltage controlled oscillator anda feedback frequency divider, an output of the voltage controlledoscillator connected to an input of the feedback frequency divider, anoutput of the feedback frequency divider coupled to an input of thevoltage controlled oscillator; and a frequency divider monitor having afirst input, a second input and an output, the first input of thefrequency divider monitor connected to the output of the voltagecontrolled oscillator and the second input of the frequency dividermonitor coupled to an output of the feedback frequency divider.

A second aspect of the present invention is a method, comprising:providing a phase locked loop circuit including a voltage controlledoscillator and a feedback frequency divider, an output of the voltagecontrolled oscillator connected to an input of the feedback frequencydivider, an output of the feedback frequency divider coupled to an inputof the phase detector; providing a frequency divider monitor having afirst input, a second input and an output, the first input of thefrequency divider monitor connected to the output of the voltagecontrolled oscillator and the second input of the frequency dividermonitor coupled to an output of the feedback frequency divider;measuring a frequency ratio of a frequency of a signal on the output ofthe voltage controlled oscillator and of a frequency of a signal on theoutput of the feedback frequency divider; and generating a alert signalin response to the frequency ratio falling outside an upper or a lowerlimit around a specified value of the frequency ratio.

BRIEF DESCRIPTION OF DRAWINGS

The features of the invention are set forth in the appended claims. Theinvention itself, however, will be best understood by reference to thefollowing detailed description of an illustrative embodiment when readin conjunction with the accompanying drawings, wherein:

FIG. 1 is block circuit diagram of a first frequency generator andmonitor circuit according to a first embodiment of the presentinvention;

FIG. 2 is block circuit diagram of a second frequency generator andmonitor circuit according to a second embodiment of the presentinvention;

FIG. 3 is block circuit diagram of a third frequency generator andmonitor circuit according to a third embodiment of the presentinvention;

FIG. 4 is a timing diagram of various signals of the circuits of FIGS.1, 2 and 3;

FIG. 5 is a circuit diagram of a first type of programmable period tovoltage converter of FIGS. 1, 2 and 3;

FIG. 6 is a circuit diagram of a second type of programmable period tovoltage converter of FIGS. 1, 2 and 3;

FIG. 7 is a circuit diagram of a third type of programmable period tovoltage converter of FIGS. 1, 2 and 3;

FIG. 8 is a additional timing diagram of various signals of the circuitsof FIGS. 1, 2 and 3;

FIG. 9 is a circuit diagram a first type of error amplifier circuit ofFIGS. 1, 2 and 3;

FIG. 10 is a circuit diagram of a second type of error amplifier circuitof FIGS. 1, 2 and 3;

FIG. 11 is a circuit diagram a comparator of FIGS. 1, 2 and 3; and

FIG. 12 is a circuit diagram a logic unit of FIGS. 1, 2 and 3.

DETAILED DESCRIPTION OF THE INVENTION

An external frequency divider is defined as a frequency divider notphysically present on the integrated circuit chip containing the phaselock loop, but it is a part of the feedback frequency divider.

A clock signal is defined as a signal having a regular repeating patternof a time period of high voltage and a time period of low voltage. Theduty cycle of a clock signal is the time duration of a high perioddivided by the time period of the clock signal. The voltage level of thelow periods is often denoted as a “0” and the voltage level of the highperiods is often denoted as “1.” Hereinafter, the signals denoted asf_(IN), f_(VCOO), f_(B), f_(OUT) and f_(EXT) are clock signals.

A frequency divider is a circuit that generates an output signal havinga frequency that is less than the frequency of the input signal. Thedivide ratio of a frequency divider is defined as the frequency of theoutput signal divided by the frequency of the input signal and is nevergreater than 1. For example, a divide by 3 frequency divider has aoutput frequency that is 1/3 that of the input frequency. It is commonfor the divide ratio to be expressed as a ratio of positive wholenumbers greater than zero.

The term identically designed is defined to mean devices (e.g.capacitors, transistors, diodes, resistors, current sources) or circuitsthat are intended to be as close to identical when fabricated aspermitted by the fabrication process used to fabricate the devices orcircuits.

FIG. 1 is the block circuit diagram of a first frequency generator andmonitor circuit 100A according to a first embodiment of the presentinvention. In FIG. 1, frequency generator and monitor circuit 100Aincludes a phase locked loop circuit which includes a phase detector105, a charge pump 110, a voltage controlled oscillator 115 whichgenerates a clock signal f_(VCOO), a forward frequency divider 120(which is optional) which generates a clock signal f_(OUT) and afeedback frequency divider 125 which generates a clock signal f_(B).

A first input of phase detector 105 is connected to clock signal f_(IN)and a second input of the phase detector is connected to an output(f_(B)) of feedback frequency divider 125. An output of phase detector105 is connected to an input of charge pump 110. An output of chargepump 110 is connected to and input of voltage controlled oscillator 115.An output (f_(VCOO)) of voltage controlled oscillator 115 is connectedto an input of forward frequency divider 120 and an input of feedbackfrequency divider 125.

Frequency generator and monitor circuit 100A also includes a frequencydivider monitor 130. Frequency divider monitor 130 includes a firstperiod generator 135A which generates a tg1o signal and a second periodgenerator 135B which generates a tg2o signal, a first period to voltageconverter 145A which generates a ptv1o from the tg1o signal and aplurality of bn/dj bit inputs and a second period to voltage converter145B which generates a ptv2o from the tg2o signal and the plurality ofbn/dj bit inputs, a decoder 150 which generate bd/djA and bd/djB bitsfrom a bit control signal, an error amplifier 155, a comparator 160having a plurality of threshold voltage inputs Vthn, and a logic unit165 generating alert signals WARN and ALARM.

Alternatively, first and second period to voltage converters 145A and145B may be designed for specific R ratios (see equation 1) and decoder150 eliminated.

An input of first period generator 135A is connected to the output(f_(VCOO)) of voltage controlled oscillator 115. An input of secondperiod generator 135B is connected to the output (f_(B)) of feedbackfrequency divider 125. An input of first period to voltage converter145A is connected to the output (tg1o) of first period generator 135A.An input of second period to voltage converter 145B is connected to theoutput (tg2o) of second period generator 135B. First and second periodgenerators 135A and 135B are identically designed. First and secondperiod to voltage converters 145A and 145B are identically designed.Bits bn/djA and bn/djB are supplied to first and second period tovoltage converters 145A and 145B respectively.

The operation of frequency divider monitor 130 is based on the fact thatthe ratio (R) of the frequency of the output signal (f_(VCOO)) ofvoltage controlled oscillator and the frequency of the output signal(f_(B)) of feedback frequency divider 125 is designed to be a constantand preset value as expressed by:f _(VCOO) /f _(B) =R   (1)

Frequency divider monitor 130 measures f_(VCOO)/f_(B) in real time andwhen f_(VCOO)/f_(B) exceeds limits set on R (i.e. exceeds R+HL or R−LLwhere HL is the maximum increase in R allowed and LL is the maximumdecrease in R allowed). A warning signal (WARN) or an alarm signal(ALARM) is generated when the limits on R are exceeded.

In FIG. 1, the value R includes only the divide ratio of feedbackfrequency divider 125. So the only frequency divider monitored byfrequency divider monitor 130 is feedback frequency divider 125.

FIG. 2 is block circuit diagram of a second frequency generator andmonitor circuit 110B according to a second embodiment of the presentinvention. Frequency generator and monitor circuit 110B is similar tofrequency generator and monitor circuit 110A (see FIG. 1) except theinput of feedback frequency divider 125 is connected to the output offorward frequency divider 120 instead of the output of voltagecontrolled oscillator 115 (see FIG. 1).

Operation of frequency generator and monitor circuit 110B is similar tothe operation of frequency generator and monitor circuit 110A (see FIG.1), but because the output (f_(VCOO)) of forward frequency divider 120is presented to the input of feedback frequency divider 125, the value Rincludes the divide ratio of forward frequency divider 120 and thedivide ratio of feedback frequency divider 125. So both forwardfrequency divider 120 and feedback frequency divider 125 are monitoredby frequency divider monitor 130.

FIG. 3 is block circuit diagram of a third frequency generator andmonitor circuit 110C according to a third embodiment of the presentinvention. Frequency generator and monitor circuit 110C is similar tofrequency generator and monitor circuit 110B (see FIG. 2) except theinput of feedback frequency divider 125 is connected to the output ofexternal frequency divider 170 instead of to the output of forwardfrequency divider 120 (see FIG. 2) and the input of external frequencydivider 170 is connected to the output of forward frequency divider 120.

Operation of frequency generator and monitor circuit 110B is similar tothe operation of frequency generator and monitor circuit 110B (see FIG.2), but because the output (f_(VCOO)) of forward frequency divider 120is presented to the input of forward frequency divider 120, the output(f_(OUT)) of forward frequency 120 is presented to the input of externalfrequency divider 170 and the output (f_(EXT)) of external frequencydivider 170 is presented to the input of feedback frequency divider 125,the value R includes the divide ratio of forward frequency divider 120,the divide ratio of feedback frequency divider 125 and the divide ratioof external frequency divider 170. So forward frequency divider 120,feedback frequency divider 125 and external frequency divider 170 aremonitored by frequency divider monitor 130.

Referring to FIGS. 1, 2 and 3, first and second period generators 135Aand 135B are one bit counters so that the half period of the generatoroutput is the period of the input regardless the duty cycle of theinput. The counter can be rising edge trigged or falling edge trigged.This is illustrated in FIG. 4.

FIG. 4 is a timing diagram of various signals of the circuits of FIGS.1, 2 and 3. In FIG. 4, the input (f_(VCOO)) to first period generator135A (see FIG. 1) has an exemplary duty cycle of 50% and the half periodof the output (tg1o) of first period generator 135A is equal to a periodof f_(VCOO). The input (f_(B)) to second period generator 135B (seeFIG. 1) has an exemplary duty cycle of 12.5% and the half period of theoutput (tg2o) of second period generator 135A is equal to a period off_(B). In FIG. 4, feedback frequency generator 125 (see FIG. 3) is anexemplary divide by four (has divide ratio of 1/4) frequency divider.The period of tg2o is four times the period of tg1o. In general, sincefrequency dividers can only divide down the input frequency (a divide by1 or divide by less than 1 frequency divider, by definition can notexist), f_(VCOO) is equal to or higher than f_(B) and the period off_(VCOO) is always equal to or shorter than that of f_(B).

FIG. 5 is a circuit diagram of a first type of programmable period tovoltage converter of FIGS. 1, 2 and 3. In FIG. 5, programmable period tovoltage converter 145A/145B includes a current mirror having a primaryside and a secondary side including a set of programmable currentfingers. Current source I0 and PFET P0 form the primary side of thecurrent mirror. PFETs P1 to Pn, P1-1 to Pn-1 and NFETs N1 to Nn form theprogrammable current fingers of the secondary side of the currentmirror. Each programmable current finger is identically designed. Eachprogrammable current finger is connected to a corresponding control bitb1 to bn. When a control bit bk (k=1,2, . . . n) is at logic high, PFETPk-1 is turned off, NFET Nk is turned on and the PFET Pk is turned onand has contribution of current I0 to the total current of Is. Whentg1o/tg2o is at logic low, PFET Pm is turned on, NFET Nm is turned off,capacitor C (includes the parasitic capacitance on the ptv1o/ptv2o) ischarged through PFET Pm by the current Is. The maximum voltage acrosscapacitor C, VCmax, is given by: $\begin{matrix}{{{VC}\quad\max} = \frac{I\quad 0*{Nif}*T}{C}} & (2)\end{matrix}$where I0 is the current level supplied by current source I0, Nif is thenumber of the programmable current fingers turned on, T is the periodtime of logic low of tg1o/tg2o and C is the total capacitance onptv1o/ptv2o. When tg1o/tg2o is at logic high, PFET Pm is turned off andNFET Nm is turned on, capacitor C is discharged. Since the dischargecurrent of capacitor C is much larger than the charge current I0 so thevoltage level on ptv1o/ptv2o drops to zero very fast.

Returning to FIGS. 1, 2 and 3, the frequency ratio R, see equation (1)supra, and the period ratio is 1/R. R programmable current fingers areturned on in programmable period to voltage converter 145A while oneprogrammable current finger is turned on in programmable period tovoltage converter 145B. More generally, $\begin{matrix}{\frac{1}{R} = \frac{NifB}{NifA}} & (3)\end{matrix}$where NifA is the number of the programmable current fingers turned onin programmable period to voltage converter 145A and NifB is the numberof the programmable current fingers turned on in programmable period tovoltage converter 145B. The VCmax of each of programmable period tovoltage converters 145A and 145B is the same.

FIG. 6 is a circuit diagram of a second type of programmable period tovoltage converter of FIGS. 1, 2 and 3. In FIG. 6, programmable period tovoltage converter 145A/45B includes a current mirror having a primaryside and a secondary side including a set of programmable capacitorfingers. Current source I0 and PFET P0 form the primary side of thecurrent mirror. PFET P1 is the secondary side of the current mirror.NFETs N1-1 to Nj-1, NFETs N1-2 to Nj-2 and capacitors C1 to Cj form theprogrammable capacitor fingers. Each programmable capacitor finger isidentically designed. Each programmable capacitor finger is connected toa corresponding control bit d1 to dj. When the control bit dk(k=1,2,j)is at logic high, the finger is selected, when dk is at logic low, thefinger is disabled. When tg1o/tg2o is at logic low, PFET Pm is turnedon, NFET Nk-1 is turned off and capacitor Ck is charged through PFET Pmby the current I0. The maximum voltage VCmax across the capacitors ofall turned on programmable capacitor fingers is given by:$\begin{matrix}{{{VC}\quad\max} = \frac{I\quad 0*T}{C*{Ncf}}} & (4)\end{matrix}$where I0 is the current level supplied by current source I0, T is theperiod time of logic low of tg1o/tg2o, C is the capacitance value thecapacitor of each finger and Ncf is the number of programmable capacitorfingers turned on. When tg1o/tg2o is at logic high, PFET Pm is turnedoff and NFET Nk-1(k=1,2, . . . j) is turned on, the capacitor Ck isdischarged. Since the discharge current of C*Ncf is much larger than thecharge current I0, the voltage level on ptv1o/ptv2o drops to zero veryfast.

Returning to FIGS. 1, 2 and 3, the frequency ratio R, see equation (1)supra, and the period ratio is 1/R. R programmable capacitor fingers areturned on in programmable period to voltage converter 145B while oneprogrammable capacitor finger is turned on in programmable period tovoltage converter 145A. More generally, $\begin{matrix}{\frac{1}{R} = \frac{NcfA}{NcfB}} & (5)\end{matrix}$where NcfA is the number of the programmable capacitor fingers turned onin programmable period to voltage converter 145A and NcfB is the numberof the programmable capacitor fingers turned on in programmable periodto voltage converter 145B. The VCmax of each of programmable period tovoltage converters 145A and 145B is the same.

FIG. 7 is a circuit diagram of a third type of programmable period tovoltage converter of FIGS. 1, 2 and 3. Programmable period to voltageconverter 145A/145B of FIG. 7 is a combination of programmable period tovoltage converters 145A/145B of FIG. 5 and of FIG. 6 and operatessimilarly. In FIG. 7, programmable period to voltage converter 145A/145Bincludes a current mirror having a primary side and a secondary side.The secondary side has a first section including a set of programmablecurrent fingers and a second section including a set of programmablecapacitor fingers. Current source 10 and PFET P0 form the primary sideof the current mirror, PFETs P1 to Pn, P1-1 to Pn-1. NFETs N1 to Nn formthe programmable current fingers of the first section of the secondaryside of the current mirror. Each programmable current finger of thefirst section is identically designed. Each programmable current fingerof the first section is connected to a corresponding control bit b1 tobn. NFETs N1-1 to Nj-1, NFETs N1-2 to Nj-2 and capacitors C1 to Cj formthe programmable capacitor fingers of the second section of thesecondary side of the current mirror. Each programmable capacitor fingerof the second section is identically designed. Each programmablecapacitor finger of the second section is connected to a correspondingcontrol bit d1 to dj. The maximum voltage VCmax across the capacitors ofall turned on programmable capacitor fingers is given by:$\begin{matrix}{{VCmax} = \frac{I\quad 0*{Nif}*T}{C*{Ncf}}} & (6)\end{matrix}$where I0 is the current level supplied by current source I0, Nif is thenumber of the programmable current fingers turned on, T is the periodtime of logic low of tg1o/tg2o, C is the capacitance value a capacitorof a programmable capacitor finger and Ncf is the number of programmablecapacitor fingers turned on.

Returning to FIGS. 1, 2 and 3, the frequency ratio R, see equation (1)supra, and the period ratio is 1/R. R programmable fingers are turned onin programmable period to voltage converter 145A while one currentfinger is turned on in programmable period to voltage converter 145B.More generally, $\begin{matrix}{R = {\frac{NcfB}{NcfA}*\frac{NifA}{NifB}}} & (7)\end{matrix}$where NcfA is the number of the programmable capacitor fingers turned onin programmable period to voltage converter 145A, NcfB is the number ofthe programmable capacitor fingers turned on in programmable period tovoltage converter 145B, NifA is the number of the programmable currentfingers turned on in programmable period to voltage converter 145A andNcfB is the number of the programmable current fingers turned on inprogrammable period to voltage converter 145B. The VCmax of each ofprogrammable period to voltage converters 145A and 145B is the same.

Decoder 150 (see FIG. 1) is a logic circuit that sets the bit values b1through bn (0 or 1) and d1 through dj (0 or 1) using a Bit Controlsignal based on the frequency divider ratios of each frequency dividerin the clock paths, feedback frequency divider 125 in FIG. 1, forwardfrequency divider 120 and feedback frequency divider 125 in FIG. 2 andforward frequency divider 120, feedback frequency divider 125 andexternal frequency divider 170 in FIG. 3.

FIG. 8 is an additional timing diagram of various signals of thecircuits of FIGS. 1, 2 and 3. In FIG. 8 waveforms for ptv1o and ptv2ohave been added to those previously shown in FIG. 4 and described supra.When equation (3) or (5) or (7) (depending on the type of programmableperiod to voltage converter used) is met, the maximum voltage of ptv1ois equal to the maximum voltage of ptv2o and the average voltage ofptv1o is equal to the average voltage of ptv2o the same period of time.For example, in FIG. 8, the areas a1+a2+a3+a4 equal the area b. However,when equation (3) or (5) or (7) is not met, then VCmax of ptv1o andptv2o is not the same, the areas a1+a2+a3+a4 are not equal to area b,and a probable malfunction of a frequency divider has occurred.

The function of error amplifier 155 (see FIG. 1) is to magnify thevoltage difference of signals ptv1o and ptv2o described supra. There aretwo types of amplifiers that may be used for error amplifier 155, a peakvoltage operational amplifier illustrated in FIG. 9 and an averagevoltage operational amplifier illustrated in FIG. 10.

FIG. 9 is a circuit diagram a first type of error amplifier circuit ofFIGS. 1, 2 and 3. In FIG. 9, an exemplary error amplifier 155 includesoperational amplifiers A1, A2, A3, A4 and A5, diodes D1 and D2,capacitors C1, C2 and C3 and resistors R1-1, R1-2, R1-3, R2-1, R2-2 andR2-3. Operational amplifier A1, diode D1 and capacitor C1 form a firstpeak detector for ptv1o. Operational amplifier A2, diode D2 andcapacitor C2 form a second peak detector for ptv2o. Amplifiers A3 and A4are high input impedance voltage followers. Resistors R1-1 and R2-1 areleakage resistors which provide a small leakage from the capacitors C1and C2 respectively so that the outputs of the peak detectors are alittle bit lower than the peak voltages (quasi peak) and work todynamically update the peak voltages detected. Resistor R1-1 and R2-1can be resistors with large resistance or small sink-current currentsources. The operational amplifier A5, and resistors R1-2, R1-3, R2-2and R2-3 form a difference amplifier whose output (ERR) is thedifference of the two peak voltages detected. Capacitor C3 is used tofilter out the voltage ripple of the quasi detectors.

FIG. 10 is a circuit diagram of a second type of error amplifier circuitof FIGS. 1, 2 and 3. In FIG. 10, an exemplary error amplifier 155includes operational amplifier A5, capacitor C3 and resistors R1-2,R1-3, R2-2 and R2-3. The operational amplifier A5 with large capacitanceC3 has much lower forward operating frequency (positive input of A5 toERR) than a feedback frequency (ERR to the negative input of A5) so thatthe output (ERR) of operational amplifier A5 is proportional to theaverage of the voltage difference between ptv1o and ptv2o.

FIG. 11 is a circuit diagram the comparator 160 of FIGS. 1, 2 and 3. InFIG. 1, comparator 160 includes four voltage comparators VC1, VC2, VC3and VC4 having corresponding negative inputs Vth1, Vth2, Vth3 and Vth4for settable threshold voltages having the relationshipVth3>Vth1>Vth2>Vth4, and corresponding outputs Vout1, Vout2, Vout 3 andVout 4. ERR is connected to the positive inputs of each of voltagecomparators VC1, VC2, VC3 and VC4.

FIG. 12 is a circuit diagram logic unit 165 of FIGS. 1, 2 and 3. In FIG.12, logic unit comprises XNOR gate X1 and XNOR gate X2. The inputs toXNOR gate X1 are Vout1 and Vout2. The inputs to XNOR gate X2 are Vout3and Vout3. The output of XNOR gate X1 is warning signal WARN. The outputof XNOR gate X2 is alarm signal ALARM. When Vout1 and Vout2 are the samelogic level, WARN goes high. When Vout3 and Vout4 are the same logiclevel, ALARM goes high.

The threshold voltages Vth1, Vth 2, Vth3 and Vth4 are selected toprovide the following function when comparator 160 is connected to logiccircuit 165.

-   (1) When ERR is lower than Vth1 and higher than Vth2, it is normal.-   (2) When ERR is higher than Vth1 or lower than Vth2, a pre warning    signal is sent out.

(3) When ERR is higher than Vth3 or lower than Vth4, a alarm signal issent out. This is detailed in Truth Table I: ERR Vout1 Vout2 Vout3 Vout4WARN ALARM Vth2 < 0 1 0 1 0 0 ERR < Vth1 Vth1 < ERR 1 1 0 1 1 0 ERR <Vth2 0 0 0 1 1 0 Vth3 < ERR 1 1 1 1 1 1 ERR < Vth4 0 0 0 0 1 1

Referring to FIG. 1, a variation of the first embodiment of the presentinvention may be used to monitor the duty cycle of feedback frequencydivider 125. If the duty cycle of feedback frequency divider 125 is tobe monitored, period generators 135A and 135B are omitted and the output(f_(VCOO)) of voltage controlled oscillator 115 is connected to theinput of first period to voltage converter 145A and the output (f_(B))of feedback frequency divider 125 is connected to the input of secondperiod to voltage converter 145B. The operation of now modifiedfrequency generator and monitor circuit 100A is similar to that ofunmodified frequency generator and monitor circuit 100A.

Thus, the embodiments of the present invention provide methods andcircuits for monitoring operation of the frequency dividers integratedcircuits and electronic systems.

The description of the embodiments of the present invention is givenabove for the understanding of the present invention. It will beunderstood that the invention is not limited to the particularembodiments described herein, but is capable of various modifications,rearrangements and substitutions as will now become apparent to thoseskilled in the art without departing from the scope of the invention.Therefore, it is intended that the following claims cover all suchmodifications and changes as fall within the true spirit and scope ofthe invention.

1. A circuit comprising: a phase locked loop circuit including a voltagecontrolled oscillator and a feedback frequency divider, an output ofsaid voltage controlled oscillator connected to an input of saidfeedback frequency divider, an output of said feedback frequency dividercoupled to an input of said voltage controlled oscillator; a frequencydivider monitor having a first input, a second input and an output, saidfirst input of said frequency divider monitor connected to said outputof said voltage controlled oscillator and said second input of saidfrequency divider monitor coupled to an output of said feedbackfrequency divider; and said frequency divider monitor including: a firstand a second period generator, each said period generator having aninput and an output, said input of said first period generator is saidfirst input of said frequency divider monitor and said input of saidsecond period generator is said second input of said frequency dividermonitor; a first and a second period to voltage converter, each periodto voltage converter having an input and an output, said input of saidfirst period to voltage converter connected to said output of said firstperiod generator and said input of said second period to voltageconverter connected to said output of said second period generator; anerror amplifier having a first input, a second input and an output, saidoutput of said first period to voltage converter connected to said firstinput of said error amplifier and said output of said second period tovoltage converter connected to said second input of said erroramplifier; and a comparator having an input and an output and aplurality of threshold voltage inputs, said output of said erroramplifier connected to said input of said comparator.
 2. The circuit ofclaim 1, wherein said first and second period generators are one-bitcounters.
 3. The circuit of claim 1, wherein said first and secondperiod to voltage converters each have a plurality of finger inputs andare identically designed current mirrors, a primary side of each currentmirror comprising a current source and a secondary side of each currentmirror comprising a plurality of fingers, corresponding fingers of saidfirst and second current mirrors connected to a same corresponding anddifferent finger input of said plurality of finger inputs.
 4. Thecircuit of claim 1, wherein said first and second period to voltageconverters are identically designed current mirrors, a primary side ofeach current mirror comprising a current source and a secondary side ofeach current mirror comprising a plurality of fingers, each fingerincluding a capacitor, corresponding fingers of said first and secondcurrent mirrors connected to a same corresponding and different fingerinput of said plurality of finger inputs.
 5. The circuit of claim 1,wherein said first and second period to voltage converters areidentically designed current mirrors, a primary side of each currentmirror comprising a current source and a secondary side, a first sectionof said secondary side of each current mirror comprising a firstplurality of fingers, a second section of said secondary side of eachcurrent mirror comprising a second plurality of fingers, each finger ofsaid second plurality of fingers including a capacitor, each finger ofsaid first and second plurality of fingers connected to a correspondingand different finger input of said plurality of finger inputs.
 6. Thecircuit of claim 1, wherein said error amplifier is a peak voltagedifference amplifier or an average voltage difference amplifier.
 7. Thecircuit of claim 1, further including: a logic unit having an input andan output, said output of said comparator connected to said input ofsaid logic unit, said output of said logic unit is said output of saidfrequency divider monitor.
 8. The circuit of claim 1, wherein: saidoutput of said voltage controlled oscillator is directly connected tosaid input of said feedback frequency divider; said output of saidvoltage controlled oscillator is coupled to an input of a forwardfrequency divider, and an output of said forward frequency divider iscoupled to said input of said feedback frequency divider; or said outputof said voltage controlled oscillator is coupled to said input of saidforward frequency divider, said output of said forward frequency divideris coupled to an input of an external frequency divider, and an outputof said external frequency divider is coupled to said input of saidfeedback frequency divider.
 9. The circuit of claim 1, said frequencydivider monitor further including a decoder, said decoder responsive toa signal indicating a designed ratio of a frequency of a signal on saidoutput of said voltage controlled oscillator and of a frequency of asignal on said output of said feedback frequency oscillator, saiddecoder having a first set of outputs connected to programmable inputssaid first period to voltage converter and a second set of outputsconnected to programmable inputs said first period to voltage converter.